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Public Release Notes for Altium Designer | Altium Designer User Manual | Documentation - Direct Placement - Beyond Mere Linking
The following sections list the release notes for publicly released versions of Altium Designer Public Release Notes for Altium Designer. Using Altium Documentation. Contents Version For a summary of new features and subsequent improvements in Altium Designer 22, see New in Altium Designer.
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Connect to Support Center for product questions. I do not want to leave feedback. A specific project was experiencing slow performance when moving net labels on its source schematics. You can now change the layer for a length tuning object through the Properties panel, using the new Layer property.
In Gerber and 3D views, countersink pads were not connecting to internal planes with the same net, when the Power Plane Connect Style was set to Direct. Incorrect drawing order meant that Annotation objects were being overlapped by any other placed view. The list of documents in a grouped tab of the Documents Bar is now sorted alphabetically. The software was being closed by Windows when dragging and dropping documents between application window instances.
When using the mention feature in a comment, the pop-up list was only using email for its search. It now populates with suggestions based on username and email. Added support for switching a repository from using SSH connection protocol to HTTPS if supported by that repository , when making a project available online.
DsnWrk document was not being saved when exiting the software. A crash would occur when trying to open a project, created through the Altium Platform Interface, from the Explorer panel for the first time. The repository structure validation has been disabled for the time being to not block project commits.
Placement of components from a Workspace Library was not possible if the time format on the PC included '. Find and Replace string substitution would cause an exception error when attempting to perform a partial string replacement. Solder Mask openings for pads were not being displayed when viewing a mirrored embedded board in 3D. Clearance Boundaries would be displayed when trying to route track in a Keepout area whose Track and Copper restrictions had been disabled. Pad Via libraries always opened with Imperial Display Units, regardless of the units chosen when the library was saved.
Pad Templates in the Properties panel were listed in the order they were added; they are now listed alphabetically. When adding one or more mechanical layers to the 'Other Layers' group, in the new Gerber Setup dialog, addition would only be to the first layer in the group.
A Board Fabrication view of a panelized PCB was only displaying polygons on one board in the embedded array, instead of all boards. The Edit command was not accessible in the Components panel when not connected to an Altium Workspace. Renaming and committing a file on one PC when already open on a second, would result in the document being removed from the project when committed from the latter. It was not possible to place a Comment on a managed schematic sheet in Altium Designer.
Changing the case of letter s in a version-controlled document name would give a VCS 'File already exists' error. When connecting to a specific Workspace with certain time and date settings, Altium Designer would display an Error dialog stating that the local time was invalid. A new warning is presented when attempting to save a managed project to the active Workspace and duplicate project files are present in the design repository.
When releasing a specific project using the Project Releaser, managed OutJob files would get unusual characters added to the beginning of a file name. When placing from the Components panel some users would see a 'Store update, insert, or delete statement affected an unexpected number of rows 0 ' error message. If the Windows decimal separator was set to the comma character, design constraints were not being imported during import of a Mentor Xpedition file.
Added the ability to present the Y-axis in Logarithmic form for simulation results in the Sim Data Editor, in the same way previously only possible for the X-axis. The following exception was being encountered: "EOleException. Object reference not set to an instance of an object in Altium. Switching to another application while in-line editing in a schematic text frame could result in the edits being lost and the message "Interactive process not finished" appearing. The Find Text dialog now includes a Mask Matching option, when enabled everything in the workspace is masked except the found results.
Formulas within text on a schematic were not being resolved correctly when the PC was set to use French regional settings for Windows. In a rigid-flex design, if the flex zone has a Coverlay layer with a layer type of Solder Mask, the actual Solder Mask layer is always displayed in the 2D view even when its visibility is disabled in the View Configuration panel.
Double-clicking on stacked PCB objects in 3D view mode with the 'Display Popup Selection dialog' option enabled and the 'Double Click Runs Interactive Properties' option disabled, would sometimes result in the software being locked in 3D view mode and not being able to save the board. The embedded board array object now includes a Board Shape option in the Properties panel; use this to switch the PCB background from green to transparent.
When pasting a via over a pad and some polygons, the selection pop-up would appear, even though there was no ambiguity as to which net that of the pad the via should 'pick up'. When the PCB.
IPCSupport advanced option is enabled, and there is a certain combination of columns enabled in the Drill Table defaults, and the Drill Table defaults are edited to include certain additional columns, those columns could become repeated in the table.
A pad with the Counterhole option enabled could result in that pad disconnecting from inner layer polygons when the Counterhole size approached the pad size. The gray-scale color palette used for generating PCB Prints did not offer the correct coloring choices. It was not possible to select any components on a particular PCB document due to a regression involving ordinate dimensions that included several points of measurement.
GerberDialog option in the Advanced Settings dialog. The settings for mechanical layers added to plots in the old Gerber Setup dialog were not retained when those Gerber settings were opened in the new Gerber Setup dialog. GerberDialog option in the Advanced Settings dialog and with the output format set to 'filename. Note that you can only copy an Annotation object when it is not attached to another Draftsman object, such as a View. Copying and pasting a table that includes merged cells would result in the merged cells becoming un-merged in the pasted table.
The Filter feature in the Components panel and the MPS panel was incorrectly displaying the temperature value options in degrees Fahrenheit instead of Celcius. The Allegro importer would sometimes incorrectly create a region object in the same shape and location as a polygon. The Allegro importer was incorrectly creating a polygon cutout over unconnected pads within a polygon, making it impossible to control the polygon clearance using design rules.
There was an issue with multi-part components where, for floating nodes, a? It was not possible to stop a running sweep-type simulation at any stage in the sweep. The performance has been increased when plotting histograms and parametric plots by a factor of The properties of an alternate varied part are now displayed as read-only in the Properties panel when that alternate part is selected on the schematic.
Toggling the visibility of pin parameters would reset their location to default. Component Pins tab of the Properties panel would not sort by Name, only by Pin number. It was not possible to configure the default visibility of Sheet Entry cross-references to not visible. Dragging the center handle on a polygon edge would not always remove that edge when it was redundant. Attempting to move a component with the mouse that was failing the component clearance rule would not show an online rule violation, even though one existed.
Outline detection was sometimes failing when the shape included a combination of arcs and tracks. After dragging and dropping a 3D model from the Explorer panel onto a footprint open for editing, and then placing a pad, a warning that the component could not be saved because a command was already active would appear when attempting to save. This no longer occurs. The PCB. ComponentSelection advanced option was not being applied, component selection was always using the contents of the Courtyard layer type.
The Pin Swapping option for routing has been disabled by default and can be enabled during each new session of Altium Designer. A new option to 'Merge regions and pads inside Footprint' has been added to the Gerber Setup dialogs. With this option enabled, regions within a footprint will be merged with pads during generation of Gerber outputs. Numerous improvements made to the Components panel, helping simplify the process of moving from file-based components to managed components.
Numerous usability improvements made to the Library Migrator, including feedback about: conflicting parameters, model checking, empty folder paths, and other areas. The Library Migrator would not always indicate the reason a component failed to import.
The validator has been improved to provide more details. Fixed typos in the 'Location of project files has changed' dialog. The Connection Manager and the Properties panel did not display the same pin numbers in a multi-board project. After editing multiple components in the Batch Component Editor, user-defined pin mapping definitions were deleted.
The Explorer panel was not presenting the aspect views for browsing detailed data for a selected item revision when using the panel's Search view. Support added to use a file-based PWL source. Attempting to open the simulation model for a component placed from a DbLib would result in an access violation. When attempting to change multiple selected components via the Properties panel, if a different library is selected as the Source, the Component Source dialog appears.
When the Select button is clicked the Replace dialog opens to choose the replacement, but instead of updating all currently selected components the Replace dialog would reappear for each of the selected components.
Updates such as footprint and parameter changes to components that were used as an alternate part in a Variant, were not propagating through to the design when an Update Schematics or Update Parameters command was run.
Improved the performance of dragging components on a schematic sheet that has a large number of components and wires. When enabled, each special string has its name displayed as a faint superscript.
Net name negation using the trailing backslash character was not working for Power Ports. An access violation would sometimes occur during differential pair routing if the PCB file was stored in a OneDrive folder.
Altium Designer - PCB Design Software
Parent page: Finalizing the Board Design. Via stitching is a technique used to tie together larger copper areas on different layers, in effect creating a strong vertical connection through the board structure, helping maintain a low impedance and short return loops. Via stitching can also be used to tie areas of copper that might otherwise be isolated from their net to that net. Via shielding has a different function, in RF designs it is used to help reduce crosstalk and electromagnetic interference in a route that is carrying an RF signal.
A via shield, also known as a via fence or a picket fence, is created by placing one or more rows of vias alongside the signal's route path. In Altium Designer, this is referred to as via shielding. Altium Designer supports both via stitching and via shielding. In the image below, shielding vias are highlighted, move the cursor over the image to highlight the stitching vias that have been added to this board. Use the Via Stitching and Via Shielding commands to stitch copper on different layers, and to add a wall of shielding vias adjacent to a route path hover to highlight shielding vias.
Via stitching is run as a post-process, filling free areas of copper with stitching vias. For via stitching to be possible, there must be overlapping regions of copper that are attached to the specified net, on different layers. Supported regions of copper include Fills, Polygons and Power Planes.
Using the selected net, the stitching algorithm identifies all Fills, Polygons and Power Planes attached to that net and attempts to connect them through the board, using the specified via and stitching pattern. Notes about the Add Stitching to Net dialog settings:. Each set of stitching vias are added to a union, set the PCB panel to Unions mode to locate and examine the vias included in a via stitching set.
A stitching set can be removed by running the Tools » Via Stitching » Remove Via Stitching Group command, then clicking on any via in that set. As well as covering the entire board, stitching vias can be constrained to a user-defined area.
When the stitching is within a user-defined area, that area of vias can be interactively moved and resized, if required. Enable the Constrain Area option to restrict stitching vias to a user-defined area. To constrain via stitching to a specific area, enable the Constrain Area checkbox in the Add Stitching to Net dialog, as shown above. As soon as you enable this option the dialog will close and the cursor will change to a crosshair, ready to define the area - note the Status bar, it will prompt Select the first point of the area.
The process of defining a via stitching area is the same as defining a solid region or a polygon, you:. Once the area is defined you will return to the Add Stitching to Net dialog, so you can configure the rest of the settings. Click OK when this is complete, Altium Designer will then analyze the area, identify potential via sites, and place the stitching vias.
The set of vias in each unique area of via stitching are clustered into a Union a set of objects that the PCB editor recognizes as a single group.
The entire union can be moved, and the area can also be resized. Drag a selection window to select a stitching area, then move or resize by positioning the mouse to get the correct cursor. The vias will be placed along both sides of the chosen net, wherever it is possible to place a via that complies with the applicable design rules.
Notes about the Add Shielding to Net dialog, and using shielding vias:. This is actually a very good rule for stitching any ground fill to the ground plane on a multi-layer design. NB: C speed of light will be approx.
As well as adding shielding vias along each side of the routing, you can also include shielding copper, as shown in the image below. To do this, enable the Add shielding copper option. This copper is created as a polygon, so it obeys the applicable Clearance and Polygon Connect Style design rules. The Add shielding copper option will add a polygon that encloses the shielding vias. The polygon edge that is away from the shielded net will touch the edge of the vias.
The polygon edge that is adjacent to the shielded net will be set back from the net by the applicable Clearance design rule. If the Add clearance cutout option is also enabled, the polygon will instead be set back from the shielded net by the Distance setting in the Add Shielding to Net dialog.
Hover the cursor over the image below to see the difference. Shielding vias around a net with the clearance cutout option enabled, move the cursor over the image to disable the clearance cutout option. The style of the connection from the shielding vias to the shielding copper polygon can be controlled by including a Polygon Connect Style design rule, targeted at the shielding vias and polygon. Use the InViaShielding query keyword to scope this design rule, so that it specifically targets those vias and that polgyon.
Each via in a stitching or shielding array is identified by the addition of a string to the net name, such as [VS1], as shown in the image below, where:.
All vias that are part of that array will select if the Select checkbox is enabled in the panel as shown in the image below. Alternatively, double click on any via in the array to open the Properties panel and edit the array. Use the PCB panel in Unions mode to select all vias in a stitching or shielding array. In this image, all four via shielding unions are selected. The properties of a stitching or shielding via set can be edited once it has been selected, in the Via Stitching or the Via Shielding mode of the Properties panel.
An example of an edit being performed to a via shielding. As soon as any property has been edited in the panel, the Changes pending message and buttons appear at the bottom of the panel - use the appropriate button to complete your editing action. The following collapsible sections contain information about the Via Shielding options and controls available:.
The following collapsible sections contain information about the Via Stitching options and controls available:.
Once stitching is complete, you will need to re-pour the polygons if the applicable Polygon Connect Style design rule specifies a relief connection style. This can be done using the commands in the Tools » Polygon Pours sub-menu. Using Altium Documentation. Shielding Parameters. Net — the net to have shielding vias placed around. Stagger alternate rows — alternate rows of shielding vias are offset by half of the Grid value when this option is enabled. Row Spacing — spacing between rows of shielding vias edge to edge separation when the Rows setting is greater than 1.
Distance — separation from the edge of the shielded net track segments, to the edge of the shielding vias. Grid — the distance between the edges of adjacent shielding vias. Shielding vias will not be placed in violation of applicable design rules; if a potential via site would result in a violation then that site is skipped. Rows — number of rows of shielding vias. Add Shielding — place a polygon over the area occupied by the shielding vias, connected to the net specified in the Via Net field.
The polygon is defined in accordance with the applicable Clearance constraint and Polygon Connect Style design rules.
Add Clearance Cutout — include a polygon cutout around the shielded net, set back from the net by the distance specified in the Distance field. Use this when you require a different clearance from the applicable Clearance constraint design rule. Net — the net being shielded by the shielding vias. Net Class — if the chosen Net is a member of a Net Class, it will be displayed in this field.
Via Template. Template — displays the currently chosen via template. Use the drop-down to change the assigned via template. Library — displays to which library the via template is linked and includes the option to Unlink the template from said library. Net — the net that the shielding vias are connected to. Via Type — use the drop-down to select the type of via from those available in the layer stack. Via Types — click to open the Layer Stack to configure the required via types for the active layer stack.
Hole Information. Hole Size — size of the hole in the shielding vias. Tolerance — negative and positive hole size tolerances allowed for the shielding vias. Size and Shape. Size and Shape — vias are one of three styles: Simple — the via diameter is the same on all layers Top-Middle-Bottom — the via diameter can be specified for the Top layer, Middle all internal layers , and Bottom layer. Full Stack — the via diameter can be specified for every signal layer.
Diameter — diameter of the shielding vias. Thermal Relief — check the Direct box then click to open the Connect Style dialog to specify the connection style. Solder Mask Expansion. Rule — enable this option to allow the existing solder mask expansion rule to take effect on the shielding vias. Manual — enable this option to edit the mask expansion values below for these shielding vias. Top — enter the required mask expansion for the Top Layer. Bottom — enter the required mask expansion for the Bottom Layer.
Top Tented — if this checkbox is enabled, the mask is closed on the Top Layer for these shielding vias. Bottom Tented — if this checkbox is enabled, the mask is closed on the Bottom Layer for these shielding vias. Linked — if the Linked option is enabled, the same expansion value is used for both the Top and Bottom layers. From Hole Edge — enable this option to calculate the mask expansion from the edge of the drill hole instead of the edge of the via donut. Stitching Parameters.
Constrain Area — enable to constrain via stitching to a specific area. After selecting the option, you will be taken to the design space. After using the cross-hair cursor to define the constrain area, right-click to return to the dialog. Edit Area — click to edit the constrain area. The stitching pattern will placed within the constrain area, starting at an offset of the specified X and Y amount.
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